Checker Design for On-line Testing of Xilinx FPGA Communication Protocols

In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemented in Xilinx FPGA based designs. A formal language enabling to describe the protocol was created for this purpose together with a generator of the formal description into VHDL code. The VHDL code can be then used for the synthesis of the checker structure and used in applications with Xilinx FPGAs.

• Type: Conference
• Year: 2007
• Where: DFT
• Authors: Martin Straka, Jiri Tobola, Zdenek Kotásek
• Keywords: Communication Protocol, Communication Protocol Testing, DFT 2007, Hardware, Xilinx Fpgas