Online Protocol Testing for FPGA Based Fault Tolerant Systems

In this paper, the methodology for automated design of checker for communication protocol testing is presented. Based on the level of checking, different design strategies can be performed - in the paper the lowest level is presented. The definition of dedicated language for the description of possible communication faults is presented. The core generator is used to produce VHDL code describing the behaviour of the checker.

• Type: Conference
• Year: 2007
• Where: DSD
• Authors: Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka
• Keywords: Communication Protocol Testing, DSD 2007, Hardware, Lowest Level, Possible Communication Faults