Checkpointing alternatives for high performance, power-aware processors

High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes unattractive in terms of resource and power requirements for future generation processors. We propose out-of-order checkpoint release and checkpoint prediction, two alternatives that require significantly less resources and power while maintaining high-performance. We demonstrate their utility at the register alias table (RAT). Our methods reduce the number of RAT checkpoints to 1/3 (from 48 down to 16) for an aggressive, 8-way superscalar processor with a 256-entry instruction window. Using a 0.18um process model we estimate that RAT power is reduced by 24%. Categories and Subject Descriptors C.1 Processor Architectures, B.8 Performance and Reliability. General Terms Algorithms, Performance, Design, Experimentation. Keywords Checkpointing, renaming, out-of-order execution, poweraware, power density.

• Type: Conference
• Year: 2003
• Where: ISLPED
• Authors: Andreas Moshovos
• Keywords: 8-way Superscalar Processor, Future Generation Processors, ISLPED 2003, Out-of-order Checkpoint Release