ISLPED 2003 - PDF Preprint Papers

ISLPED 2003 International Symposium on Low Power Electronics and Design

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ISLPED
2003
ACM

197views Hardware» more ISLPED 2003»

Analyzing the energy consumption of security protocols

14 years 5 months ago

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Security is critical to a wide range of wireless data applications and services. While several security mechanisms and protocols have been developed in the context of the wired In...

Nachiketh R. Potlapally, Srivaths Ravi, Anand Ragh...

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Id	Views	Title	Status

1	197	Analyzing the energy consumption of security protocols	claim
2	155	Low-power high-level synthesis for FPGA architectures	claim
3	152	An MTCMOS design methodology and its application to mobile computing	claim
4	149	Elements of low power design for integrated systems	claim
5	142	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization	claim
6	138	An environmental energy harvesting framework for sensor networks	claim
7	129	A critical analysis of application-adaptive multiple clock processors	claim
8	127	Lightweight set buffer: low power data cache for multimedia application	claim
9	122	Analysis of discharge techniques for multiple battery systems	claim
10	122	A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores	claim
11	115	Reducing energy and delay using efficient victim caches	claim
12	113	Reducing power density through activity migration	claim
13	111	Energy-aware memory allocation in heterogeneous non-volatile memory systems	claim
14	111	A low-power VLSI architecture for turbo decoding	claim
15	109	Energy optimization techniques in cluster interconnects	claim
16	102	Energy-aware architectures for a real-valued FFT implementation	claim
17	100	Checkpointing alternatives for high performance, power-aware processors	claim
18	96	Effective graph theoretic techniques for the generalized low power binding problem	claim
19	95	Microarchitecture level power and thermal simulation considering temperature dependent leakage model	claim
20	95	Power efficient comparators for long arguments in superscalar processors	claim
21	95	Power-aware scheduling of conditional task graphs in real-time multiprocessor systems	claim
22	94	Evolution of low power electronics and its future applications	claim
23	94	A 0.75-mW analog processor IC for wireless biosignal monitor	claim
24	91	Reducing reorder buffer complexity through selective operand caching	claim
25	90	Design methodology for fine-grained leakage control in MTCMOS	claim
26	90	Understanding and minimizing ground bounce during mode transition of power gating structures	claim
27	90	Low cost instruction cache designs for tag comparison elimination	claim
28	88	Energy-efficient data scrambling on memory-processor interfaces	claim
29	88	Reducing data cache energy consumption via cached load/store queue	claim
30	87	On load latency in low-power caches	claim
31	86	Exploiting compiler-generated schedules for energy savings in high-performance processors	claim
32	85	Energy recovery clocking scheme and flip-flops for ultra low-energy applications	claim
33	85	ILP-based optimization of sequential circuits for low power	claim
34	85	Low power coordination in wireless ad-hoc networks	claim
35	83	Leakage power modeling and optimization in interconnection networks	claim
36	82	Multivoltage scheduling with voltage-partitioned variable storage	claim
37	81	A clock delayed sleep mode domino logic for wide dynamic OR gate	claim
38	80	Level conversion for dual-supply systems	claim
39	80	A selective filter-bank TLB system	claim
40	78	Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies	claim
41	77	Microprocessor pipeline energy analysis	claim
42	73	A power-aware SWDR cell for reducing cache write power	claim
43	71	Strained-si devices and circuits for low-power applications	claim
44	68	Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning	claim
45	63	Voltage scheduling under unpredictabilities: a risk management paradigm	claim
46	59	Exploiting program hotspots and code sequentiality for instruction cache leakage management	claim

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