Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding

This paper describes a dynamic voltage and frequency scaling (DVFS) technique for MPEG decoding to reduce the energy consumption using the computational workload decomposition. This technique decomposes the workload for decoding a frame into onchip and off-chip workloads. The execution time required for the onchip workload is CPU frequency-dependent, whereas the off-chip workload execution time does not change, regardless of the CPU frequency, resulting in the maximum energy savings by setting the minimum frequency during off-chip workload execution time, without causing any delay penalty. This workload decomposition is performed using a performance-monitoring unit (PMU) in the XScale-processor, which provides various statistics such as cache hit/miss and CPU stall, due to data dependency at run time. The onchip workload for an incoming frame is predicted using a framebased history so that the processor voltage and frequency can be scaled to provide the exact amount of computing power...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Kihwan Choi, Ramakrishna Soma, Massoud Pedram
• Keywords: DAC 2004, Design Automation, Off-chip Workload Execution, Workload Execution Time, Workload Prediction Error