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DAC 2004 Design Automation Conference

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DAC
2004
ACM

227views Computer Architecture» more DAC 2004»

A new heuristic algorithm for reversible logic synthesis

14 years 11 months ago

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Reversible logic has applications in many fields, including quantum computing. Synthesis techniques for reversible circuits are not well developed, even for functions with a small...

Pawel Kerntopf

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Id	Views	Title	Status

1	227	A new heuristic algorithm for reversible logic synthesis	claim
2	225	Abstraction of assembler programs for symbolic worst case execution time analysis	claim
3	222	Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding	claim
4	198	Worst-case circuit delay taking into account power supply variations	claim
5	193	Automated fixed-point data-type optimization tool for signal processing and communication systems	claim
6	191	Area-efficient instruction set synthesis for reconfigurable system-on-chip designs	claim
7	190	A method to decompose multiple-output logic functions	claim
8	190	An SoC design methodology using FPGAs and embedded microprocessors	claim
9	183	Accurate pre-layout estimation of standard cell characteristics	claim
10	180	Dynamic FPGA routing for just-in-time FPGA compilation	claim
11	180	Statistical gate delay model considering multiple input switching	claim
12	176	Toward a methodology for manufacturability-driven design rule exploration	claim
13	171	SUNMAP: a tool for automatic topology selection and generation for NoCs	claim
14	168	Refining the SAT decision ordering for bounded model checking	claim
15	165	CAD challenges in BioMEMS design	claim
16	163	Heterogeneous MP-SoC: the solution to energy-efficient signal processing	claim
17	163	STAC: statistical timing analysis with correlation	claim
18	162	Benefits and challenges for platform-based design	claim
19	159	Defining coverage views to improve functional coverage analysis	claim
20	155	Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs	claim
21	155	Communication-efficient hardware acceleration for fast functional simulation	claim
22	154	FPGA power reduction using configurable dual-Vdd	claim
23	154	Fast and accurate parasitic capacitance models for layout-aware	claim
24	153	Fast statistical timing analysis handling arbitrary delay correlations	claim
25	152	Automated design of operational transconductance amplifiers using reversed geometric programming	claim
26	152	A new state assignment technique for testing and low power	claim
27	151	Multi-profile based code compression	claim
28	150	Defect tolerant probabilistic design paradigm for nanotechnologies	claim
29	150	Abstraction refinement by controllability and cooperativeness analysis	claim
30	149	Statistical optimization of leakage power considering process variations using dual-Vth and sizing	claim
31	148	Automatic generation of breakpoint hardware for silicon debug	claim
32	147	Automated energy/performance macromodeling of embedded software	claim
33	146	An analytical approach for dynamic range estimation	claim
34	145	DyAD: smart routing for networks-on-chip	claim
35	145	Enabling energy efficiency in via-patterned gate array devices	claim
36	144	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory	claim
37	144	Design optimizations for microprocessors at low temperature	claim
38	144	Efficient on-line testing of FPGAs with provable diagnosabilities	claim
39	144	Debugging HW/SW interface for MPSoC: video encoder system design case study	claim
40	143	Proxy-based task partitioning of watermarking algorithms for reducing energy consumption in mobile devices	claim
41	143	Multiple constant multiplication by time-multiplexed mapping of addition chains	claim
42	143	A dual-core 64b ultraSPARC microprocessor for dense server applications	claim
43	141	Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics	claim
44	140	Architecture-level synthesis for automatic interconnect pipelining	claim
45	139	Placement feedback: a concept and method for better min-cut placements
46	137	Virtual memory window for application-specific reconfigurable coprocessors	claim
47	137	Parametric yield estimation considering leakage variability	claim
48	137	Hierarchical approach to exact symbolic analysis of large analog circuits	claim
49	136	Adaptive data partitioning for ambient multimedia	claim
50	135	Post-layout logic optimization of domino circuits	claim
51	134	Design automation for mask programmable fabrics	claim
52	133	Retargetable profiling for rapid, early system-level design space exploration	claim
53	133	Characterizing embedded applications for instruction-set extensible processors	claim
54	133	Extending the transaction level modeling approach for fast communication architecture exploration	claim
55	133	Implicit pseudo boolean enumeration algorithms for input vector control	claim
56	132	Fast and flexible buffer trees that navigate the physical layout environment	claim
57	132	Quantum logic synthesis by symbolic reachability analysis	claim
58	132	Synthesizing interconnect-efficient low density parity check codes	claim
59	131	Practical repeater insertion for low power: what repeater library do we need?	claim
60	130	A methodology to improve timing yield in the presence of process variations	claim
61	129	A SAT-based algorithm for reparameterization in symbolic simulation	claim
62	128	Toward a systematic-variation aware timing methodology	claim
63	128	ORACLE: optimization with recourse of analog circuits including layout extraction	claim
64	128	Theoretical and practical limits of dynamic voltage scaling	claim
65	128	Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining	claim
66	128	Correct-by-construction layout-centric retargeting of large analog designs	claim
67	127	The best of both worlds: the efficient asynchronous implementation of synchronous specifications	claim
68	126	Automatic abstraction and verification of verilog models	claim
69	126	Efficient power/ground network analysis for power integrity-driven design methodology	claim
70	126	Automatic generation of equivalent architecture model from functional specification	claim
71	126	Low voltage swing logic circuits for a Pentium 4 processor integer core	claim
72	124	Circuit-aware architectural simulation	claim
73	124	A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits	claim
74	123	An integrated hardware/software approach for run-time scratchpad management	claim
75	123	On test generation for transition faults with minimized peak power dissipation	claim
76	122	Automatic translation of software binaries onto FPGAs	claim
77	122	Divide-and-concatenate: an architecture level optimization technique for universal hash functions	claim
78	121	Energy characterization of filesystems for diskless embedded systems	claim
79	121	A frequency relaxation approach for analog/RF system-level simulation	claim
80	121	Memory access scheduling and binding considering energy minimization in multi-bank memory systems	claim
81	120	Compact thermal modeling for temperature-aware design	claim
82	120	Leakage in nano-scale technologies: mechanisms, impact and design considerations	claim
83	119	Profile-guided microarchitectural floorplanning for deep submicron processor design	claim
84	119	Security as a new dimension in embedded system design	claim
85	118	Introduction of local memory elements in instruction set extensions	claim
86	118	Leakage aware dynamic voltage scaling for real-time embedded systems	claim
87	117	A method for correcting the functionality of a wire-pipelined circuit	claim
88	117	Reducing clock skew variability via cross links	claim
89	116	Efficient equivalence checking with partitions and hierarchical cut-points	claim
90	116	Modular scheduling of guarded atomic actions	claim
91	116	Quadratic placement using an improved timing model	claim
92	115	Passivity-preserving model reduction via a computationally efficient project-and-balance scheme	claim
93	114	Exploiting structure in symmetry detection for CNF	claim
94	114	An approach to placement-coupled logic replication	claim
95	114	Optical proximity correction (OPC): friendly maze routing	claim
96	114	Probabilistic regression suites for functional verification	claim
97	113	Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions	claim
98	113	A recursive paradigm to solve Boolean relations	claim
99	113	System level leakage reduction considering the interdependence of temperature and leakage	claim
100	113	Symmetry detection for incompletely specified functions	claim
101	112	A novel approach for flexible and consistent ADL-driven ASIP design	claim
102	111	System design for DSP applications in transaction level modeling paradigm	claim
103	108	High level cache simulation for heterogeneous multiprocessors	claim
104	106	Leakage-and crosstalk-aware bus encoding for total power reduction	claim
105	106	Energy-aware deterministic fault tolerance in distributed real-time embedded systems	claim
106	105	Performance analysis of different arbitration algorithms of the AMBA AHB bus	claim
107	105	Pre-layout wire length and congestion estimation	claim
108	105	A general decomposition strategy for verifying register renaming	claim
109	105	Efficient timing closure without timing driven placement and routing	claim
110	103	Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era	claim
111	103	Large-scale full-wave simulation	claim
112	103	Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects	claim
113	103	AMUSE: a minimally-unsatisfiable subformula extractor	claim
114	103	An efficient finite-domain constraint solver for circuits	claim
115	103	Specific scheduling support to minimize the reconfiguration overhead of dynamically reconfigurable hardware	claim
116	101	A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits	claim
117	101	Industrial experience with test generation languages for processor verification	claim
118	99	Selective gate-length biasing for cost-effective runtime leakage control	claim
119	99	Statistical timing analysis based on a timing yield model	claim
120	97	Data compression for improving SPM behavior	claim
121	95	Profile-based optimal intra-task voltage scheduling for hard real-time applications	claim
122	95	On path-based learning and its applications in delay test and diagnosis	claim
123	94	Static timing analysis using backward signal propagation	claim
124	94	First-order incremental block-based statistical timing analysis	claim
125	88	Large-scale placement by grid-warping	claim
126	84	A timing-driven module-based chip design flow	claim
127	81	FITS: framework-based instruction-set tuning synthesis for embedded application specific processors	claim

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