Circuit-aware architectural simulation

Architectural simulation has achieved a prominent role in the system design cycle by providing designers the ability to quickly examine a wide variety of design choices. However, the recent trend in system design toward architectures that react to circuit-level phenomena has outstripped the capabilities of traditional cycle-based architectural simulators. In this paper, we present an architectural simulator design that incorporates a circuit modeling capability, permitting architectural-level simulations that react to circuit characteristics (such as latency, energy, or current draw) on a cycle-by-cycle basis. While these additional capabilities slow simulation speed, we show that the careful application of circuit simulation optimizations and simulation sampling techniques permit high levels of detail with sufficient speed to examine entire workloads. Categories and Subject Descriptors B.8.2 [Performance Analysis and Design Aids]: Architectural Simulation; B.5.2 [Register-Transfer-Le...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge
• Keywords: Circuit Simulation Optimizations, DAC 2004, Design Automation, Keywords Architectural Simulation, Slow Simulation Speed