Clock buffer polarity assignment for power noise reduction

Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: 1) partitioning; 2) 2-coloring on minimum spanning tree; and 3) recursive minmatching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 50% and 51%, respectively.

• Type: Conference
• Year: 2006
• Where: ICCAD
• Authors: Rupak Samanta, Ganesh Venkataraman, Jiang Hu
• Keywords: Clock, Clock Network, Clock Tree, Hardware, ICCAD 2006