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ITC
2003
IEEE

CMOS Built-In Test Architecture for High-Speed Jitter Measurement

14 years 5 months ago
CMOS Built-In Test Architecture for High-Speed Jitter Measurement
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution of 70ps RMS jitter occupying 0.0575mm2 area.
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ITC
Authors Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz
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