A CMOS integrated linear voltage-to-pulse-delay-time converter for time based analog-to-digital converters

A novel 0. 13,um CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC ml architecture uses current starved inverters where the inverter delay versus input voltage characteristic is linearized by using Vcik Vclk-delayed several parallel current starving devices with different gate bias voltages and different amounts of source degeneration. The VTC M2 operates at a clock frequency of up to 500 MHz. Input voltage signals of up to 2 GHz can be converted to pulse time delays by using several VTC's in parallel. Since the voltage to time Vin d M3 conversion is essentially done with a single inverter stage no I sample-and-hold is needed for the input voltage. The VTC can be used in combination with a time-to-digital converter (TDC) to

• Type: Conference
• Year: 2006
• Where: ISCAS
• Authors: Holly Pekau, A. Yousif, James W. Haslett
• Keywords: Input Voltage, Input Voltage Characteristic, ISCAS 2006, VTC Ml Architecture