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ISCAS 2006 International Symposium on Circuits and Systems

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ISCAS
2006
IEEE

222views Hardware» more ISCAS 2006»

Texture image retrieval using complex directional filter bank

14 years 6 months ago

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— In this paper, the shift-invariant complex directional ﬁlter bank (CDFB) is proposed for texture image retrieval. By combining the Laplacian pyramid and the CDFB, a new image...

An P. N. Vo, Truong T. Nguyen, Soontorn Oraintara

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Id	Views	Title	Status

1	222	Texture image retrieval using complex directional filter bank	claim
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3	206	JPEG2000 image coding system theory and applications	claim
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16	154	A novel Fisher discriminant for biometrics recognition: 2DPCA plus 2DFLD	claim
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61	120	Localization based audio source separation by sub-band beamforming	claim
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63	119	Localized microarchitecture-level voltage management	claim
64	119	Performance improvement of the H.264/AVC deblocking filter using SIMD instructions	claim
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68	118	An ultra-low power silicon-on-sapphire ADC for energy-scavenging sensors	claim
69	118	Complex network topologies and synchronization	claim
70	118	A robust continuous-time multi-dithering technique for laser communications using adaptive optics	claim
71	117	Embedded image coding using quincunx directional filter bank	claim
72	116	Wavelet based detection of moving tree branches and leaves in video	claim
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74	116	Neural network stream processing core (NnSP) for embedded systems	claim
75	116	Underdetermined sparse source separation of convolutive mixtures with observation vector clustering	claim
76	116	An asynchronous delta-sigma converter implementation	claim
77	115	Performance comparison of LDPC-coded FBMC and CP-OFDM in beyond 3G context	claim
78	114	System for deposition and characterization of polypyrrole/gold bilayer hinges	claim
79	114	Characterization of a metastability measurement system	claim
80	113	High speed routing lookup IC design for IPv6	claim
81	113	Low power state-parallel relaxed adaptive Viterbi decoder design and implementation	claim
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86	112	Inductance extraction for general interconnect structures	claim
87	112	Silicon neurons that inhibit to synchronize	claim
88	111	Spike response properties of an AER EAR	claim
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95	109	Network-on-chip quality-of-service through multiprotocol label switching	claim
96	109	Feature-oriented multiple description image coding	claim
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100	108	DSP engine design for LINC wireless transmitter systems
101	108	Design of optimal quincunx filter banks for image coding	claim
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107	107	Assessment of probability density estimation methods: Parzen window and finite Gaussian mixtures	claim
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110	106	A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time	claim
111	106	Mismatch compensation techniques using random data for time-interleaved A/D converters	claim
112	106	A novel approach to L2-sensitivity minimization of digital filters subject to L2-scaling constraints	claim
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114	105	Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs	claim
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118	104	Performance of time-frequency localized and frequency selective filter banks in multicarrier systems	claim
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125	102	On-chip bidirectional transceiver	claim
126	102	Eigenvector algorithms using reference signals for blind source separation of instantaneous mixtures	claim
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130	101	Bidirectional conversion to minimum signed-digit representation	claim
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142	98	Effects of crosstalk noise on H-tree clock distribution networks	claim
143	98	Towards rate-distortion tradeoff in real-time color video coding	claim
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145	98	The effect of switch resistance on pipelined ADC MDAC settling time	claim
146	97	Supercritical stability in a sonar receiver circuit	claim
147	97	A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264	claim
148	96	In-scale motion aligned temporal filtering	claim
149	96	Approximately linear-phase recursive digital filters with variable magnitude characteristics	claim
150	96	Frame-level data reuse for motion-compensated temporal filtering	claim
151	96	On the initialization of the DNMF algorithm	claim
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153	95	Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking	claim
154	95	Vertex cache of programmable geometry processor for mobile multimedia application	claim
155	94	Relaxed tree search MIMO signal detection algorithm design and VLSI implementation	claim
156	94	Implementation of digital IQ imbalance compensation in OFDM WLAN receivers	claim
157	94	On the sensitivity of BDDs with respect to path-related objective functions	claim
158	93	A one-shot projection method for interconnects with process variations	claim
159	93	Radial distribution power flow studies in a remotely distributed environment	claim
160	93	Discontinuity-induced bifurcations in TCP/RED communication algorithms	claim
161	93	A low-power clock frequency multiplier	claim
162	93	Phase-tracking loop based on delta-sigma oversampling architecture	claim
163	92	The optimal MAC layer for low-power UWB is non-coordinated	claim
164	92	Time-sliding suboptimal regulation of bilinear interconnected systems	claim
165	92	Model of a true random number generator aimed at cryptographic applications	claim
166	91	DSP architecture for cochlear implants	claim
167	91	Average rate behavior for cooperative diversity in wireless networks	claim
168	90	A novel ternary more, less and equality circuit using recharged semi-floating gate devices	claim
169	90	Feature competition in a spike-based winner-take-all VLSI network	claim
170	90	Quality-biased rate allocation for compound image coding with block classification	claim
171	90	Phase measurement and adjustment of digital signals using random sampling technique	claim
172	90	On flash A/D-converters with low-precision comparators	claim
173	88	Application of fluid time hopping coding to multiple access in ultra wide band sensor networks	claim
174	88	An aVLSI recurrent network of spiking neurons with reconfigurable and plastic synapses	claim
175	88	SiP integration of intelligent, adaptive, self-sustaining power management solutions for portable applications	claim
176	87	Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier	claim
177	87	A generalized deterministic algorithm for blind channel identification with filter bank precoders	claim
178	87	NoC monitoring: impact on the design flow	claim
179	87	Error-resilience transcoding using content-aware intra-refresh based on profit tracing	claim
180	86	Fast timing analysis of plane circuits via two-layer CNN-based modeling	claim
181	85	Effective tunneling capacitance: a new metric to quantify transient gate leakage current	claim
182	85	Digital phase-shift modulation for an isolation buffer in silicon-on-sapphire CMOS	claim
183	85	Low-power Q-enhancement for parallel LC tanks	claim
184	85	Power-adaptive operational amplifier with positive-feedback self biasing	claim
185	85	Analog frequency response measurement in mixed-signal systems	claim
186	84	Transmission line based FIR structures for high speed adaptive equalization	claim
187	84	Power supply variation effects on timing characteristics of clocked registers	claim
188	84	Programmable synaptic weights for an aVLSI network of spiking neurons	claim
189	84	One-dimensional interpolation based channel estimation for mobile DVB-H reception	claim
190	83	Performance-driven crosstalk elimination at post-compiler level	claim
191	83	Nonylphenol biodegradation kinetics estimation using neural networks	claim
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195	81	Equivalent output-filtering using fast QRD-RLS algorithm for burst-type training applications	claim
196	81	Fully programmable bias current generator with 24 bit resolution per bias	claim
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198	80	A fast state-space algorithm to estimate harmonic distortion in fully differential weakly nonlinear Gm-C filters	claim
199	80	Fundamental limitations of continuous-time delta-sigma modulators due to clock jitter	claim
200	79	Spike timing dependent adaptation for mismatch compensation	claim
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202	79	A low-power 64-point FFT/IFFT design for IEEE 802.11a WLAN application	claim
203	78	A low power SoC bus with low-leakage and low-swing technique	claim
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205	77	Modeling orientation selectivity using a neuromorphic multi-chip system	claim
206	77	Electro-chemical multi-channel integrated neural interface technologies	claim
207	77	A parallel search algorithm for CLNS addition optimization	claim
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213	74	Low-power hybrid turbo decoding based on reverse calculation	claim
214	74	NIUGAP: low latency network interface architecture with Gray code for networks-on-chip	claim
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216	72	On the two-dimensional orthogonal drawing of series-parallel graphs	claim
217	71	Spectral response improvement of CMOS APS pixel through lateral collection	claim
218	70	A portable all-digital pulsewidth control loop for SOC applications	claim
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220	70	Power aware learning for class AB analogue VLSI neural network	claim
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224	67	A single inductor multiple output converter with adaptive delta current mode control	claim
225	66	Switch synchronizing delayed feedback control for piecewise linear systems	claim
226	66	Competing and accommodating behaviors of peace SOM	claim
227	65	Precoded V-BLAST for ISI MIMO channels	claim
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230	54	Modeling of switched DC-DC converters by mixed s-z description	claim

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