Code compression for low power embedded system design

erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the degree of freedom is still very high. However, a major drawback in system-level optimization is the complexity of the design space as a result of the vast amount of possible parameters. In order to conduct efficient system-level optimizations, powerful design space exploration is required. This paper describes our approach for system-level power optimization, namely code compression. We show that code compression does not only reduce main memory size requirements, but can also reduce reduce significantly the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. We will show that we save power and also reduce the overall chip area while maintaining or even improving performance. Previous work in code compression, which has not simulated p...

• Type: Conference
• Year: 2000
• Where: DAC
• Authors: Haris Lekatsas, Jörg Henkel, Wayne Wolf
• Keywords: Code Compression, Code Compression Basics, DAC 2000, Design Automation, System-level Power Optimization