Designers of distributed embedded systems face many challenges in determining the appropriate tradeoffs to make when defining a system architecture or retargeting an existing design. Communication synthesis, the automatic generation of the necessary software and hardware needed for system components to exchange data, is required to more effectively explore the design space and automate what are very error-prone tasks. This work examines the problem of mapping a high-level specification to an arbitrary architecture that uses specific, common bus protocols for interprocessor communication. A communication model is presented that allows for easy retargeting to different bus topologies and protocols and illustrates that global considerations are necessary to achieve a correct implementation. An algorithm is presented that partitions multi-hop communication timing constraints to effectively utilize the bus bandwidth along a communication path. The communication synthesis tool is fully inte...
Ross B. Ortega, Gaetano Borriello