ICCAD 1998 - PDF Preprint Papers

ICCAD 1998 International Conference on Computer-Aided Design

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ICCAD
1998
IEEE

196views Hardware» more ICCAD 1998»

Analysis of watermarking techniques for graph coloring problem

14 years 3 months ago

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We lay out a theoretical framework to evaluate watermarking techniques for intellectual property protection (IPP). Based on this framework, we analyze two watermarking techniques ...

Gang Qu, Miodrag Potkonjak

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Id	Views	Title	Status

1	196	Analysis of watermarking techniques for graph coloring problem	claim
2	168	On-line scheduling of hard real-time tasks on variable voltage processor	claim
3	153	Intellectual property protection by watermarking combinational logic synthesis solutions	claim
4	143	Real-time operating systems for embedded computing	claim
5	130	GPCAD: a tool for CMOS op-amp synthesis	claim
6	122	Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits	claim
7	120	Communication synthesis for distributed embedded systems	claim
8	117	CONCERT: a concurrent transient fault simulator for nonlinear analog circuits	claim
9	116	On primitive fault test generation in non-scan sequential circuits	claim
10	112	Using precomputation in architecture and logic resynthesis	claim
11	109	CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems	claim
12	107	Techniques for energy minimization of communication pipelines	claim
13	105	Fanout optimization under a submicron transistor-level delay model	claim
14	101	Wireplanning in logic synthesis	claim
15	100	Architecture driven circuit partitioning	claim
16	98	Determination of worst-case aggressor alignment for delay calculation	claim
17	96	Test set compaction algorithms for combinational circuits	claim
18	95	Control generation for embedded systems based on composition of modal processes	claim
19	95	Efficient analog circuit synthesis with simultaneous yield and robustness optimization	claim
20	94	Noise considerations in circuit optimization	claim
21	93	Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation	claim
22	92	Slicing floorplans with pre-placed modules	claim
23	90	Technology mapping for domino logic	claim
24	87	Gate-size selection for standard cell libraries	claim
25	87	Full-chip verification of UDSM designs	claim
26	86	Polynomial methods for component matching and verification	claim
27	84	Using a single input to support multiple scan chains	claim
28	83	Signature hiding techniques for FPGA intellectual property protection	claim
29	83	Lazy transition systems: application to timing optimization of asynchronous circuits	claim
30	82	Symbolic model checking of process networks using interval diagram techniques	claim
31	81	A simultaneous routing tree construction and fanout optimization algorithm	claim
32	80	On the optimization power of retiming and resynthesis transformations	claim
33	79	Reencoding for cycle-time minimization under fixed encoding length	claim
34	76	Functional debugging of systems-on-chip	claim
35	75	Efficient encoding for exact symbolic automata-based scheduling	claim
36	75	A fast, accurate, and non-statistical method for fault coverage estimation	claim
37	74	Synthesis of application specific instructions for embedded DSP software	claim
38	71	Dynamic power management of electronic systems	claim
39	71	High-level variable selection for partial-scan implementation	claim
40	70	Verification by approximate forward and backward reachability	claim
41	66	Tight integration of combinational verification methods	claim
42	65	Multiway partitioning with pairwise movement	claim
43	64	Energy-efficiency in presence of deep submicron noise	claim

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