A comparison of three verification techniques: directed testing, pseudo-random testing and property checking

This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bristol was introducing pseudo-random testing (using Specman) and property checking (using GateProp) into their verification flows and thus provides a good opportunity to compare these two techniques with the existing strategy of directed testing using VHDL bus functional models. Categories and Subject Descriptors B.5.2 [Register-Transfer-Level Implementation]: Design Aids ? Verification. General Terms Verification.

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Mike Bartley, Darren Galpin, Tim Blackmore
• Keywords: DAC 2002, Design Automation, General Terms Verification, Infineon Technologies Design, Verification Flows