DAC 2002 - PDF Preprint Papers

DAC 2002 Design Automation Conference

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DAC
2002
ACM

233views Computer Architecture» more DAC 2002»

A comparison of three verification techniques: directed testing, pseudo-random testing and property checking

15 years 12 days ago

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This paper describes the verification of two versions of a bridge between two on-chip buses. The verification was performed just as the Infineon Technologies Design Centre in Bris...

Mike Bartley, Darren Galpin, Tim Blackmore

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Id	Views	Title	Status

1	233	A comparison of three verification techniques: directed testing, pseudo-random testing and property checking	claim
2	179	High-Level specification and automatic generation of IP interface monitors	claim
3	171	Exploiting operation level parallelism through dynamically reconfigurable datapaths	claim
4	170	Combined BEM/FEM substrate resistance modeling	claim
5	169	A physical model for the transient response of capacitively loaded distributed rlc interconnects	claim
6	162	A solenoidal basis method for efficient inductance extraction	claim
7	161	Analysis of power consumption on switch fabrics in network routers	claim
8	152	DRG-cache: a data retention gated-ground cache for low power	claim
9	152	Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique	claim
10	151	Design of a high-throughput low-power IS95 Viterbi decoder	claim
11	149	Automatic data migration for reducing energy consumption in multi-bank memory systems	claim
12	148	Deriving a simulation input generator and a coverage metric from a formal specification	claim
13	143	Software synthesis from synchronous specifications using logic simulation techniques	claim
14	142	Exploiting shared scratch pad memory space in embedded multiprocessor systems	claim
15	142	A flexible accelerator for layer 7 networking applications	claim
16	140	A framework for evaluating design tradeoffs in packet processing architectures	claim
17	138	Energy estimation and optimization of embedded VLIW processors based on instruction clustering	claim
18	137	Dynamic hardware plugins in an FPGA with partial run-time reconfiguration	claim
19	136	False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation	claim
20	136	Guaranteed passive balancing transformations for model order reduction	claim
21	135	Watermarking integer linear programming solutions	claim
22	134	Scheduler-based DRAM energy management	claim
23	134	Congestion-driven codesign of power and signal networks	claim
24	132	A universal technique for fast and flexible instruction-set architecture simulation	claim
25	131	Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver	claim
26	131	A fast on-chip profiler memory	claim
27	129	Communication architecture based power management for battery efficient system design	claim
28	128	Compiler-directed scratch pad memory hierarchy design and management	claim
29	127	A general probabilistic framework for worst case timing analysis	claim
30	126	The next chip challenge: effective methods for viable mixed technology SoCs	claim
31	126	IP delivery for FPGAs using Applets and JHDL	claim
32	124	An energy saving strategy based on adaptive loop parallelization	claim
33	123	Implementing asynchronous circuits using a conventional EDA tool-flow	claim
34	122	Transformation rules for designing CNOT-based quantum circuits	claim
35	116	ILP-based engineering change	claim
36	116	A factorization-based framework for passivity-preserving model reduction of RLC systems	claim
37	114	Hole analysis for functional coverage data	claim
38	114	Efficient code synthesis from extended dataflow graphs for multimedia applications	claim
39	114	The wearable motherboard: a framework for personalized mobile information processing (PMIP)	claim
40	113	Transformation based communication and clock domain refinement for system design	claim
41	112	A fast optical propagation technique for modeling micro-optical systems	claim
42	111	Component-based design approach for multicore SoCs	claim
43	111	Complex library mapping for embedded software using symbolic algebra	claim
44	110	Embedded software-based self-testing for SoC design	claim
45	108	An integer linear programming based approach for parallelizing applications in On-chip multiprocessors	claim
46	108	Traffic analysis for on-chip networks design of multimedia applications	claim
47	106	Uncertainty-aware circuit optimization	claim
48	103	Challenges and opportunities in electronic textiles modeling and optimization	claim
49	102	Remembrance of circuits past: macromodeling by data mining in large analog design spaces	claim
50	101	A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator	claim
51	101	Constraint-driven communication synthesis	claim
52	100	Using embedded FPGAs for SoC yield improvement	claim
53	99	Timed compiled-code simulation of embedded software for performance analysis of SOC design	claim
54	98	Tools or users: which is the bigger bottleneck?	claim
55	98	RTL c-based methodology for designing and verifying a multi-threaded processor	claim
56	95	Retargetable binary utilities	claim
57	95	Solving difficult SAT instances in the presence of symmetry	claim
58	95	Can BDDs compete with SAT solvers on bounded model checking?	claim
59	95	Schedulability of event-driven code blocks in real-time embedded systems	claim
60	95	River PLAs: a regular circuit structure	claim
61	95	Towards global routing with RLC crosstalk constraints	claim
62	94	HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery	claim
63	93	Model design using hierarchical web-based libraries	claim
64	93	Petri net modeling of gate and interconnect delays for power estimation	claim
65	92	Model composition for scheduling analysis in platform design	claim
66	92	A detailed cost model for concurrent use with hardware/software co-design	claim
67	91	TCG-S: orthogonal coupling of P*-admissible representations for general floorplans	claim
68	89	Satometer: how much have we searched?	claim
69	89	Few electron devices: towards hybrid CMOS-SET integrated circuits	claim
70	89	Unlocking the design secrets of a 2.29 Gb/s Rijndael processor	claim
71	88	Energy exploration and reduction of SDRAM memory systems	claim
72	88	System-level performance optimization of the data queueing memory management in high-speed network processors	claim
73	86	Fast three-level logic minimization based on autosymmetry	claim
74	86	Efficient state representation for symbolic simulation	claim
75	86	S-Tree: a technique for buffered routing tree synthesis	claim
76	85	Model order reduction for strictly passive and causal distributed systems	claim
77	82	A novel wavelet transform based transient current analysis for fault detection and localization	claim
78	81	An optimal voltage synthesis technique for a power-efficient satellite application	claim
79	76	Enhancing test efficiency for delay fault testing using multiple-clocked schemes	claim
80	70	Self-referential verification of gate-level implementations of arithmetic circuits	claim
81	67	Software-based diagnosis for processors	claim
82	67	System design methodologies for a wireless security processing platform	claim

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