Compilation techniques for energy reduction in horizontally partitioned cache architectures

Horizontally partitioned data caches are a popular architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. Horizontally partitioned caches help reduce cache pollution and thereby improve performance. Consequently most previous research has focused on exploiting horizontally partitioned data caches to improve performance, and achieve energy reduction only as a byproduct of performance improvement. In constrast, in this paper we show that optimizing for performance tradesoff several opportunities for energy reduction. Our experiments on a HP iPAQ h4300-like memory subsystem demonstrate that optimizing for energy consumption results in up to 127% less memory subsystem energy consumption than the performance optimal solution. Furthermore, we show that

• Type: Conference
• Year: 2005
• Where: CASES
• Authors: Aviral Shrivastava, Ilya Issenin, Nikil Dutt
• Keywords: CASES 2005, Data Caches, Energy Consumption, Energy Reduction, System Software