Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures

In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that support operations on superwords, i.e., aggregate objects consisting of several machine words. We treat the large superword register file as a compiler-controlled cache, thus avoiding unnecessary memory accesses by exploiting reuse in superword registers. This research is distinguished from previous work on exploiting reuse in scalar registers because it considers not only temporal but also spatial reuse. As compared to optimizations to exploit reuse in cache, the compiler must also manage replacement, and thus, explicitly name registers in the generated code. We describe an implementation of our approach integrated with a compiler that exploits superword-level parallelism (SLP). We present a set of results derived automatically on 4 multimedia kernels and 2 scientific benchmarks. Our results show

• Type: Conference
• Year: 2002
• Where: IEEEPACT
• Authors: Jaewook Shin, Jacqueline Chame, Mary W. Hall
• Keywords: Distributed And Parallel Computing, IEEEPACT 2002, Reuse, Superword Registers, Unnecessary Memory Accesses