IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
Memory performance is increasingly determining microprocessor performance and technology trends are exacerbating this problem. Most architectures use set-associative caches with L...
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
Information about instruction criticality can be used to control the application of micro-architectural resources efficiently. To this end, several groups have proposed methods t...
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
In this paper, we describe an algorithm and implementation of locality optimizations for architectures with instruction sets such as Intel’s SSE and Motorola’s AltiVec that su...
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
IEEEPACT
2002
IEEE
14 years 5 months ago
2002
IEEE
Researchers have studied hybrid branch predictors that leverage the strengths of multiple stand-alone predictors. The common theme among the proposed techniques is a selection mec...