Compiler-generated communication for pipelined FPGA applications

In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targeted for an FPGA with multiple external memories. For this purpose, we extend array data-flow analysis techniques from parallelizing compilers to identify pipeline stages, required inter-pipeline stage communication, and opportunities to find a minimal program execution time by trading communication overhead with the amount of computation overlap in different stages. Using the results of this analysis, we automatically generate application-specific pipelined FPGA hardware designs. We use a sample image processing kernel to illustrate these concepts. Our algorithm finds a solution in which transmitting a row of an array between pipeline stages per communication instance leads to a speedup of

• Type: Conference
• Year: 2003
• Where: DAC
• Authors: Heidi E. Ziegler, Mary W. Hall, Pedro C. Diniz
• Keywords: Application-specific Pipelined Fpga, Array Data-flow Analysis, DAC 2003, Design Automation, Pipeline Stages