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DAC 2003 Design Automation Conference

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DAC
2003
ACM

282views Computer Architecture» more DAC 2003»

Non-iterative switching window computation for delay-noise

14 years 4 months ago

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Bhavana Thudi, David Blaauw

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Id	Views	Title	Status

1	282	Non-iterative switching window computation for delay-noise	claim
2	260	Clock-tree power optimization based on RTL clock-gating	claim
3	248	Performance-impact limited area fill synthesis	claim
4	205	Behavioral consistency of C and verilog programs using bounded model checking	claim
5	198	Crosstalk noise in FPGAs	claim
6	191	A retargetable micro-architecture simulator	claim
7	181	A survey of techniques for energy efficient on-chip communication	claim
8	178	Automated synthesis of efficient binary decoders for retargetable software toolkits	claim
9	175	Data communication estimation and reduction for reconfigurable systems	claim
10	175	Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL	claim
11	173	Automatic trace analysis for logic of constraints	claim
12	173	Accurate timing analysis by modeling caches, speculation and their interaction	claim
13	173	An O(nlogn) time algorithm for optimal buffer insertion	claim
14	171	A complexity effective communication model for behavioral modeling of signal processing applications	claim
15	170	A low-energy chip-set for wireless intercom	claim
16	168	Instruction set compiled simulation: a technique for fast and flexible instruction set simulation	claim
17	167	Symbolic analysis of analog circuits with hard nonlinearity	claim
18	166	Efficient model order reduction including skin effect	claim
19	166	Performance trade-off analysis of analog circuits by normal-boundary intersection	claim
20	165	Coverage directed test generation for functional verification using bayesian networks	claim
21	164	A transformation based algorithm for reversible logic synthesis	claim
22	164	4G terminals: how are we going to design them?	claim
23	162	NORM: compact model order reduction of weakly nonlinear systems	claim
24	161	On-chip logic minimization	claim
25	161	Design of a 10GHz clock distribution network using coupled standing-wave oscillators	claim
26	161	Test generation for designs with multiple clocks	claim
27	160	Energy-aware MPEG-4 FGS streaming	claim
28	160	Analog and RF circuit macromodels for system-level analysis	claim
29	157	A 1.3GHz fifth generation SPARC64 microprocessor	claim
30	157	Energy reduction techniques for multimedia applications with tolerance to deadline misses	claim
31	157	A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference	claim
32	157	Low-power design methodology for an on-chip bus with adaptive bandwidth capability	claim
33	156	Using estimates from behavioral synthesis tools in compiler-directed design space exploration	claim
34	156	Implications of technology scaling on leakage reduction techniques	claim
35	155	Advanced techniques for RTL debugging	claim
36	154	Death, taxes and failing chips	claim
37	153	Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system	claim
38	152	Quantum-dot cellular automata: computing by field polarization	claim
39	151	Extending the lifetime of a network of battery-powered mobile devices by remote processing: a markovian decision-based approach	claim
40	151	Improved indexing for cache miss reduction in embedded systems	claim
41	150	Pushing ASIC performance in a power envelope	claim
42	149	Random walks in a supply network	claim
43	148	State-based power analysis for systems-on-chip	claim
44	148	Global resource sharing for synthesis of control data flow graphs on FPGAs	claim
45	148	Dynamic hardware/software partitioning: a first approach	claim
46	146	Architecture-level performance evaluation of component-based embedded systems	claim
47	145	Microarchitecture evaluation with physical planning	claim
48	145	A hybrid SAT-based decision procedure for separation logic with uninterpreted functions	claim
49	143	Embedded intelligent SRAM	claim
50	142	Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing	claim
51	141	Interconnect and noise immunity design for the Pentium 4 processor	claim
52	141	Distributed sleep transistor network for power reduction	claim
53	140	The synthesis of cyclic combinational circuits	claim
54	140	Design techniques for sensor appliances: foundations and light compass case study	claim
55	140	Compiler-generated communication for pipelined FPGA applications	claim
56	140	Fast timing-driven partitioning-based placement for island style FPGAs	claim
57	139	Checking satisfiability of a conjunction of BDDs	claim
58	139	Scalable modeling and optimization of mode transitions based on decoupled power management architecture	claim
59	139	Dos and don'ts of CTL state coverage estimation	claim
60	138	Instruction encoding synthesis for architecture exploration using hierarchical processor models	claim
61	137	A cost-driven lithographic correction methodology based on off-the-shelf sizing tools	claim
62	137	Test cost reduction for SOCs using virtual TAMs and lagrange multipliers	claim
63	136	High-level synthesis of asynchronous systems by data-driven decomposition	claim
64	135	Parameter variations and impact on circuits and microarchitecture	claim
65	133	Temporofunctional crosstalk noise analysis	claim
66	133	Partial task assignment of task graphs under heterogeneous resource constraints	claim
67	132	Timing optimization of FPGA placements by logic replication	claim
68	132	A TBR-based trajectory piecewise-linear algorithm for generating accurate low-order models for nonlinear analog circuits and MEMS	claim
69	132	Efficient compression and application of deterministic patterns in a logic BIST architecture	claim
70	130	Support vector machines for analog circuit performance representation	claim
71	130	Learning from BDDs in SAT-based bounded model checking	claim
72	129	Optimal integer delay budgeting on directed acyclic graphs	claim
73	129	A scalable software-based self-test methodology for programmable processors	claim
74	129	Large-scale SOP minimization using decomposition and functional properties	claim
75	129	A new enhanced constructive decomposition and mapping algorithm	claim
76	129	Synthesizing optimal filters for crosstalk-cancellation for high-speed buses	claim
77	129	Using a formal specification and a model checker to monitor and direct simulation	claim
78	129	Determining appropriate precisions for signals in fixed-point IIR filters	claim
79	128	Schedulers as model-based design elements in programmable heterogeneous multiprocessors	claim
80	128	Power grid reduction based on algebraic multigrid principles	claim
81	127	An algebraic multigrid solver for analytical placement with layout based clustering	claim
82	127	Symbolic representation with ordered function templates	claim
83	127	Statistical timing for parametric yield prediction of digital integrated circuits	claim
84	127	Realizable parasitic reduction using generalized Y-Delta transformation	claim
85	127	Test application time and volume compression through seed overlapping	claim
86	124	Multilevel global placement with retiming	claim
87	124	Automating the design of an asynchronous DLX microprocessor	claim
88	123	Improved global routing through congestion estimation	claim
89	123	SAT-based unbounded symbolic model checking	claim
90	119	Force directed mongrel with physical net constraints	claim
91	118	Seed encoding with LFSRs and cellular automata	claim
92	116	An IDF-based trace transformation method for communication refinement	claim
93	116	Vector potential equivalent circuit based on PEEC inversion	claim
94	116	Realizable RLCK circuit crunching	claim
95	115	Generalized cofactoring for logic function evaluation	claim
96	115	A timing-accurate modeling and simulation environment for networked embedded systems	claim
97	114	A fast pseudo-boolean constraint solver	claim
98	114	Multilevel floorplanning/placement for large-scale modules using B*-trees	claim
99	113	Automatic application-specific instruction-set extensions under microarchitectural constraints	claim
100	113	Optimizations for a simulator construction system supporting reusable components	claim
101	111	Making cyclic circuits acyclic	claim
102	111	Power-aware issue queue design for speculative instructions	claim
103	111	An adaptive window-based susceptance extraction and its efficient implementation	claim
104	109	Model order reduction of nonuniform transmission lines using integrated congruence transform	claim
105	107	Shatter: efficient symmetry-breaking for boolean satisfiability	claim
106	106	A tool for describing and evaluating hierarchical real-time bus scheduling policies	claim
107	100	How to make efficient communication, collaboration, and optimization from system to chip	claim

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