Complexity dichotomy on degree-constrained VLSI layouts with unit-length edges

Deciding whether an arbitrary graph admits a VLSI layout with unit-length edges is NP-complete [1], even when restricted to binary trees [7]. However, for certain graphs, the problem is polynomial or even trivial. A natural step, outstanding thus far, was to provide a broader classification of graphs that make for polynomial or NP-complete instances. We provide such a classification based on the set of vertex degrees in the input graphs, yielding a comprehensive dichotomy on the complexity of the problem, with and without the restriction to trees.

• Type: Journal
• Year: 2010
• Where: ENDM
• Authors: Vinícius G. P. de Sá, Celina M. Herrera de Figueiredo, Guilherme Dias da Fonseca, Raphael Machado
• Keywords: Arbitrary Graph, ENDM 2010, Unit-length Edges, VLSI Layout