A Comprehensive SoC Design Methodology for Nanometer Design Challenges

SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex design challenges in silicon which were not seen in higher geometries. The most commonly talked about factor is the dominance of interconnects over cell delays for long nets. Also leakage power at sub-nanometer levels is becoming a major component of the total chip power. Cross-coupling capacitance is starting to dominate and signal integrity methodologies and sign-off have become mandatory part of all sub-nanometer flows. Methodologies which can address capacity issues have also become mandatory with average design sizes crossing 10M gates for sub-nanometer processes. Traditional bottom-up based approaches alone will not suffice to handle this kind of capacity. Finally another prime factor is related to manufacturability and dealing with process variations to ensure maximum yield. In fact optimization for yie...

• Type: Conference
• Year: 2006
• Where: VLSID
• Authors: R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopal, N. Guruprasad, K. Subbarangaiah, Taher Abbasi, D. V. R. Murthy, P. Krishna Prasad, D. R. Gude
• Keywords: Computer Architecture, Design Flow, Design Methodology Flow, Nanometer Process Geometries, VLSID 2006