Concurrent Error Detection in Linear Analog Circuits Using State Estimation

We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in general, much smaller than a duplicate of the circuit under test. The error detection circuit monitors the input and some judiciously selected observable internal nodes of the examined circuit to produce an estimate of its output. In error-free operation, this estimate converges to the actual output value in a time interval that can be controlled to be sufficiently small. From then onwards, it follows exactly the output. The estimate is constructed such that it does not converge in the presence of errors and, thus, concurrent error detection is performed by comparing the two signals through an analog checker. The derived theory is validated through representative simulations on two filter examples.

• Type: Conference
• Year: 2003
• Where: ITC
• Authors: Haralampos-G. D. Stratigopoulos, Yiorgos Makris
• Keywords: Concurrent Error Detection, Error Detection, Error Detection Circuit, Hardware, ITC 2003