Constraint extraction for pseudo-functional scan-based delay testing

Recent research results have shown that the traditional structural testing for delay and crosstalk faults may result in over-testing due to the non-trivial number of such faults that are untestable in the functional mode while testable in the test mode. This paper presents a pseudo-functional test methodology that attempts to minimize the over-testing problem of the scan-based circuits for the delay faults. The first pattern of a two-pattern test is still delivered by scan in the test mode but the pattern is generated in such a way that it does not violate the functional constraints extracted from the functional logic. In this paper, we use a SAT solver to extract a set of functional constraints which consists of illegal states and internal signal correlation. Along with the functional justification (also called broad-side) test application scheme, the functional constraints are imposed to a commercial delay-fault ATPG tool to generate pseudofunctional delay tests. The experimental re...

• Type: Conference
• Year: 2005
• Where: ASPDAC
• Authors: Yung-Chieh Lin, Feng Lu, Kai Yang, Kwang-Ting Cheng
• Keywords: ASPDAC 2005, Delay Faults, Functional Constraints, Hardware, Test Mode