On the Construction of Small Fully Testable Circuits with Low Depth

During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small while circuits with low depth are often larger regarding the area requirements. A different optimization goal is good testability which can usually only be achieved by additional hardware overhead. In this paper we propose a synthesis technique that allows to trade-off between area and delay. Moreover, the resulting circuits are 100% testable under the stuck-at fault model. The proposed approach relies on the combination of 100% testable circuits derived from binary decision diagrams and 2-SPP networks. Full testability under the stuck-at fault model is proven and experimental results show the trade-off between area and depth.

• Type: Conference
• Year: 2007
• Where: DSD
• Authors: Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler
• Keywords: DSD 2007, Hardware, Optimization Goal, Stuck-at Fault Model, Testability