The universal underlying assumption made today is that Systems on chip must maintain 100% correctness regardless of the application. This work advocates the concept that some appl...
Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Dja...
We present a component-based framework and its supporting simulation tool for joint software-hardware modelling and performance analysis of multiprocessor embedded systems. This j...
We compare the complexity of "internal" and "external" equivalence checking. The former is meant for proving the correctness of a synthesis transformation by w...
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
This paper presents the architecture of a small university satellite that we have developed. The main design criteria were low cost and fault tolerance, which have been achieved b...
Dante Del Corso, Claudio Passerone, Leonardo Maria...
— Programmable multiprocessor systems-on-chip are becoming the preferred implementation platform for embedded streaming applications. This enables using more software components,...
Peter Poplavko, Twan Basten, Jef L. van Meerbergen
Design space exploration is used to shorten the design time of System-on-Chips (SoCs). The models used in the exploration need to be both accurate and fast to simulate. This paper...
— This paper presents the state-of-the-art in the field of network-on-chip (NoC) benchmarking and comparison. The study identifies the mainstream approaches, how NoCs are curre...
An address generator produces a unique address from 1 to k for the input that matches to one of k registered vectors, and produces 0 for other inputs. This paper presents the supe...