A controller-based design-for-testability technique for controller-data path circuits

This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controller and the data path parts are individually 100% testable, the composite circuit may not be easily testable by gate-level sequential ATPG. Analysis shows that a primary problem in test pattern generation of combined controller-data path circuits is the correlation of control signals due to implications imposed by the controller specification. A design-for-testability technique is developed to re-design the controller such that the implications which may produce conflicts during test pattern generation are eliminated. The DFT technique involves adding extra control vectors to the controller. Experimental results show the ability of the controller DFT technique to produce highly testable controller-data path circuits, with nominal hardware overhead.

• Type: Conference
• Year: 1995
• Where: ICCAD
• Authors: Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
• Keywords: Controller Dft Technique, Controller-data Path Circuits, Hardware, ICCAD 1995, Test Pattern Generation