Coordinated control of multiple prefetchers in multi-core systems

Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of different cores on a chip multiprocessor (CMP) can cause significant interference with prefetch and demand accesses of other cores. Because existing prefetcher throttling techniques do not address this prefetcher-caused inter-core interference, aggressive prefetching in multi-core systems can lead to significant performance degradation and wasted bandwidth consumption. To make prefetching effective in CMPs, this paper proposes a low-cost mechanism to control prefetcher-caused inter-core interference by dynamically adjusting the aggressiveness of multiple cores’ prefetchers in a coordinated fashion. Our solution consists of a hierarchy of prefetcher aggressiveness control structures that combine per-core (local) and prefetcher-caused intercore (global) interference feedback to maximize the benefits of prefet...

• Type: Conference
• Year: 2009
• Where: MICRO
• Authors: Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt
• Keywords: Aggressive Prefetching, Hardware, MICRO 2009, Prefetcher Aggressiveness Control, Prefetcher-caused Inter-core Interference