MICRO 2009 - PDF Preprint Papers

MICRO 2009 IEEE/ACM International Symposium on Microarchitecture

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MICRO
2009
IEEE

507views Hardware» more MICRO 2009»

Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling

14 years 7 months ago

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Phase Change Memory (PCM) is an emerging memory technology that can increase main memory capacity in a cost-effective and power-efﬁcient manner. However, PCM cells can endure on...

Moinuddin K. Qureshi, John Karidis, Michele France...

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Id	Views	Title	Status

1	507	Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling	claim
2	326	DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage	claim
3	315	Control flow obfuscation with information flow tracking	claim
4	222	Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping	claim
5	207	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy	claim
6	191	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches	claim
7	178	Improving cache lifetime reliability at ultra-low voltages	claim
8	168	Ordering decoupled metadata accesses in multiprocessors	claim
9	160	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor	claim
10	159	Adaptive line placement with the set balancing cache	claim
11	148	Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance	claim
12	147	Complexity effective memory access scheduling for many-core accelerator architectures	claim
13	144	Characterizing flash memory: anomalies, observations, and applications	claim
14	137	ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem	claim
15	134	Coordinated control of multiple prefetchers in multi-core systems	claim
16	134	A case for dynamic frequency tuning in on-chip networks	claim
17	133	A tagless coherence directory	claim
18	132	Finding concurrency bugs with context-aware communication graphs	claim
19	132	EazyHTM: eager-lazy hardware transactional memory	claim
20	129	Execution leases: a hardware-supported mechanism for enforcing strong non-interference	claim
21	129	In-network coherence filtering: snoopy coherence without broadcasts	claim
22	128	mSWAT: low-cost hardware fault detection and diagnosis for multicore systems	claim
23	124	ZerehCache: armoring cache architectures in high defect density technologies	claim
24	122	Characterizing the resource-sharing levels in the UltraSPARC T2 processor	claim
25	121	Improving memory bank-level parallelism in the presence of prefetching	claim
26	121	Application-aware prioritization mechanisms for on-chip networks	claim
27	120	SCARAB: a single cycle adaptive routing and bufferless network	claim
28	120	Tribeca: design for PVT variations with local recovery and fine-grained adaptation	claim
29	120	Offline symbolic analysis for multi-processor execution replay	claim
30	120	Reducing peak power with a table-driven adaptive processor core	claim
31	115	SHARP control: controlled shared cache management in chip multiprocessors	claim
32	113	Portable compiler optimisation across embedded programs and microarchitectures using machine learning	claim
33	113	The BubbleWrap many-core: popping cores for sequential acceleration	claim
34	103	BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support	claim
35	99	Low-cost router microarchitecture for on-chip networks	claim

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