Core architecture optimization for heterogeneous chip multiprocessors

Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics – no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cor...

• Type: Conference
• Year: 2006
• Where: IEEEPACT
• Authors: Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
• Keywords: Hardware, Heterogeneous Multi-core Architectures, IEEEPACT 2006, Multi-core Architecture, Pre-existing Cores