IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
Multiprocessor operating systems (OSs) pose several unique and conflicting challenges to System Virtual Machines (System VMs). For example, most existing system VMs resort to gan...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
Static Single Assignment (SSA) has become the intermediate program representation of choice in most modern compilers because it enables efficient data flow analysis of scalars an...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
Packet forwarding is a memory-intensive application requiring multiple accesses through a trie structure. The efficiency of a cache for this application critically depends on the ...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
The role of the operating system (OS) in managing shared resources such as CPU time, memory, peripherals, and even energy is well motivated and understood [23]. Unfortunately, one...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
This paper presents an automated performance tuning solution, which partitions a program into a number of tuning sections and finds the best combination of compiler options for e...
IEEEPACT
2006
IEEE
14 years 5 months ago
2006
IEEE
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...