Coverage-driven automatic test generation for uml activity diagrams

Due to the increasing complexity of today’s embedded systems, the analysis and validation of such systems is becoming a major challenge. UML is gradually adopted in the embedded system design as a system level specification. One of the major bottlenecks in the validation of UML activity diagrams is the lack of automated techniques for directed test generation. This paper proposes an automated test generation approach for the UML activity diagrams. The contribution of this paper is the use of specification coverage to generate properties as well as design models to enable directed test generation using model checking. Our experimental results demonstrate that our approach can drastically reduce the validation effort in both specification and implementation levels. Categories and Subject Descriptors: I.6.4 Simulation and ModelingModel Validation and Analysis General Terms: Verification

• Type: Conference
• Year: 2008
• Where: GLVLSI
• Authors: Mingsong Chen, Prabhat Mishra, Dhrubajyoti Kalita
• Keywords: Directed Test Generation, GLVLSI 2008, Test Generation, UML Activity Diagrams, VLSI