GLVLSI
2008
IEEE
2008
IEEE
Simultaneous optimization of memory configuration and code allocation for low power embedded systems
14 years 18 days ago
This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a dynamic power conscious region which uses low Vdd and Vth and 2) a static power ...
GLVLSI
2008
IEEE
14 years 18 days ago
2008
IEEE
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
GLVLSI
2008
IEEE
14 years 18 days ago
2008
IEEE
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
The main contribution of this work is an analytical model for finding the upper bound on the temperature difference among various locations on the die. The proposed model can be u...
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
GLVLSI
2008
IEEE
14 years 1 months ago
2008
IEEE
This paper presents a process variation tolerant, SoC ready, 1GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologie...
GLVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it i...
GLVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the ...
GLVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
GLVLSI
2008
IEEE
14 years 7 months ago
2008
IEEE
This paper presents in-order pulsed charge recycling to reduce energy consumption in an off-chip data bus. The proposed technique performs charge recycling by employing three step...