Coverage Metrics for Formal Verification

In formal verification, we verify that a system is correct with respect to a specification. Even when the system is proven to be correct, there is still a question of how complete the specification is, and whether it really covers all the behaviors of the system. The challenge of making the verification process as exhaustive as possible is even more crucial in simulation-based verification, where the infeasible task of checking all input sequences is replaced by checking a test suite consisting of a finite subset of them. It is very important to measure the exhaustiveness of the test suite, and indeed, there has been an extensive research in the simulation-based verification community on coverage metrics, which provide such a measure. It turns out that no single measure can be absolute, leading to the development of numerous coverage metrics whose usage is determined by industrial verification methodologies. On the other hand, prior research of coverage in formal verification has focus...

• Type: Conference
• Year: 2003
• Where: CHARME
• Authors: Hana Chockler, Orna Kupferman, Moshe Y. Vardi
• Keywords: CHARME 2003, Coverage Metrics, Formal Verification, Hardware, Simulation-based Verification