A criticality-driven microarchitectural three dimensional (3D) floorplanner

- As technology scales, interconnect delays begin to dominate the performance of modern microprocessors. The ability to reduce the length of global wires has become an important design constraint, however only a subset of those global wires is critical for determining performance.

• Type: Conference
• Year: 2009
• Where: ASPDAC
• Authors: Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan
• Keywords: ASPDAC 2009, Global Wires, Hardware, Important Design Constraint, Modern Microprocessors