ASPDAC 2009 - PDF Preprint Papers

ASPDAC 2009 Asia and South Pacific Design Automation Conference

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ASPDAC
2009
ACM

262views Hardware» more ASPDAC 2009»

Fault modeling and testing of retention flip-flops in low power designs

14 years 7 months ago

Download gra103.aca.ntu.edu.tw

Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...

Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...

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Id	Views	Title	Status

1	262	Fault modeling and testing of retention flip-flops in low power designs	claim
2	255	A low-power FPGA based on autonomous fine-grain power-gating	claim
3	249	Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model	claim
4	212	Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography	claim
5	190	A reverse-encoding-based on-chip AHB bus tracer for efficient circular buffer utilization	claim
6	184	FastRoute 4.0: global router with efficient via minimization	claim
7	174	Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications	claim
8	171	A current-mode DC-DC converter using a quadratic slope compensation scheme	claim
9	164	Accounting for non-linear dependence using function driven component analysis	claim
10	164	Gen-Adler: the Generalized Adler's equation for injection locking analysis in oscillators	claim
11	164	High-performance global routing with fast overflow reduction	claim
12	161	Risk aversion min-period retiming under process variations	claim
13	160	CAD challenges for 3D ICs	claim
14	159	Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors	claim
15	155	Variation-aware resource sharing and binding in behavioral synthesis	claim
16	153	A 3D prototyping chip based on a wafer-level stacking technology	claim
17	152	A novel Toffoli network synthesis algorithm for reversible logic	claim
18	152	A control theory approach for thermal balancing of MPSoC	claim
19	150	Using a dataflow abstracted virtual prototype for HdS-design	claim
20	145	A multilevel analytical placement for 3D ICs	claim
21	145	High performance on-chip differential signaling using passive compensation for global communication	claim
22	144	Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis	claim
23	143	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method	claim
24	142	On the futility of statistical power optimization	claim
25	141	Parallelizing fundamental algorithms such as sorting on multi-core processors for EDA acceleration	claim
26	141	Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures	claim
27	139	Hardware-dependent software synthesis for many-core embedded systems	claim
28	137	Ultra low-power ANSI S1.11 filter bank for digital hearing aids	claim
29	137	Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture	claim
30	135	Analysis of communication delay bounds for network on chips	claim
31	133	A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor	claim
32	132	A cycle-based synthesis algorithm for reversible logic	claim
33	131	A 1 GHz CMOS comparator with dynamic offset control technique	claim
34	130	Analog placement with common centroid and 1-D symmetry constraints	claim
35	127	Timing driven power gating in high-level synthesis	claim
36	127	A criticality-driven microarchitectural three dimensional (3D) floorplanner	claim
37	125	A dynamic quality-scalable H.264 video encoder chip	claim
38	124	Fast false path identification based on functional unsensitizability using RTL information	claim
39	124	Thermal optimization in multi-granularity multi-core floorplanning	claim
40	122	Tolerating process variations in high-level synthesis using transparent latches	claim
41	122	Accelerating statistical static timing analysis using graphics processing units	claim
42	120	Path selection for monitoring unexpected systematic timing effects	claim
43	119	A Time-to-Digital Converter with small circuitry	claim
44	118	Automatic instrumentation of embedded software for high level hardware/software co-simulation	claim
45	117	Adaptive techniques for overcoming performance degradation due to aging in digital circuits	claim
46	117	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications	claim
47	115	Automatic formal verification of clock domain crossing signals	claim
48	115	Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform	claim
49	115	Incremental and on-demand random walk for iterative power distribution network analysis	claim
50	115	Scheduled voltage scaling for increasing lifetime in the presence of NBTI	claim
51	115	Frequent value compression in packet-based NoC architectures	claim
52	114	Exploring adjacency in floorplanning	claim
53	114	Flexible and abstract communication and interconnect modeling for MPSoC	claim
54	113	Post-routing redundant via insertion with wire spreading capability	claim
55	112	Compiler-managed register file protection for energy-efficient soft error reduction	claim
56	111	Exact and fast L1 cache simulation for embedded systems	claim
57	111	A UML-based approach for heterogeneous IP integration	claim
58	110	A software solution for dynamic stack management on scratch pad memory	claim
59	110	Variability-aware robust design space exploration of chip multiprocessor architectures	claim
60	109	Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints	claim
61	109	Soft lists: a native index structure for NOR-flash-based embedded devices	claim
62	108	CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction	claim
63	108	SAT-controlled redundancy addition and removal: a novel circuit restructuring technique	claim
64	108	Synthesis of networks on chips for 3D systems on chips	claim
65	105	Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radio	claim
66	105	Fast circuit simulation on graphics processing units	claim
67	105	Design and chip implementation of the ubiquitous processor HCgorilla	claim
68	104	Addressing thermal and power delivery bottlenecks in 3D circuits	claim
69	102	Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction	claim
70	102	Novel task migration framework on configurable heterogeneous MPSoC platforms	claim
71	100	A wireless real-time on-chip bus trace system	claim
72	100	Noise minimization during power-up stage for a multi-domain power network	claim
73	99	From restrictive to prescriptive design	claim
74	98	Needs and trends in embedded software development for consumer electronics	claim
75	95	A multi-task-oriented security processing architecture with powerful extensibility	claim
76	92	Hybrid LZA: a near optimal implementation of the leading zero anticipator	claim
77	91	Thermal-aware post compilation for VLIW architectures	claim
78	91	Bound-based identification of timing-violating paths under variability	claim
79	80	Improving scalability of model-checking for minimizing buffer requirements of synchronous dataflow graphs	claim

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