Cyclostationary feature detection on a tiled-SoC

In this paper, a two-step methodology is introduced to analyse the mapping of Cyclostationary Feature Detection (CFD) onto a multi-core processing platform. In the first step, the tasks to be executed by each core are determined in a structured way using techniques known from the design of array processors. In the second step, the implementation of tasks on a processing core is analysed. Using this methodology, it is shown that calculating a 127 × 127 Discrete Spectral Correlation Function requires approximately 140 µs on a tiled System on Chip (SoC) with 4 Montium cores.

• Type: Conference
• Year: 2007
• Where: DATE
• Authors: André B. J. Kokkeler, Gerard J. M. Smit, Thijs Krol, Jan Kuper
• Keywords: Cyclostationary Feature Detection, DATE 2007, Hardware, Multi-core Processing Platform, Two-step Methodology