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DATE
2007
IEEE

223views Hardware» more DATE 2007»

CARAT: a toolkit for design and performance analysis of component-based embedded systems

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Solid frameworks and toolkits for design and analysis of embedded systems are of high importance, since they enable early reasoning about critical properties of a system. This pap...

Egor R. V. Bondarev, Michel R. V. Chaudron, Peter ...

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Id	Views	Title	Status

1	223	CARAT: a toolkit for design and performance analysis of component-based embedded systems	claim
2	185	An ILP formulation for system-level application mapping on network processor architectures	claim
3	184	New safety critical radio altimeter for airbus and related design flow	claim
4	174	ATLAS: a chip-multiprocessor with transactional memory support	claim
5	173	Analytical router modeling for networks-on-chip performance analysis	claim
6	173	Architectural leakage-aware management of partitioned scratchpad memories	claim
7	172	Diagnosis, modeling and tolerance of scan chain hold-time violations	claim
8	172	DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems	claim
9	167	A decomposition-based constraint optimization approach for statically scheduling task graphs with communication delays to multiprocessors	claim
10	165	Boosting the role of inductive invariants in model checking	claim
11	164	Distributed power-management techniques for wireless network video systems	claim
12	160	FPGA-based networking systems for high data-rate and reliable in-vehicle communications	claim
13	157	Energy evaluation of software implementations of block ciphers under memory constraints	claim
14	156	Process variation tolerant low power DCT architecture	claim
15	155	A novel technique to use scratch-pad memory for stack management	claim
16	155	Design fault directed test generation for microprocessor validation	claim
17	154	Soft error rate analysis for sequential circuits	claim
18	150	A low-SER efficient core processor architecture for future technologies	claim
19	150	Assessing carbon nanotube bundle interconnect for future FPGA architectures	claim
20	150	Fast memory footprint estimation based on maximal dependency vector calculation	claim
21	148	Temperature aware task scheduling in MPSoCs	claim
22	146	Data-flow transformations using Taylor expansion diagrams	claim
23	146	DFM/DFY: should you trust the surgeon or the family doctor?	claim
24	145	Using an innovative SoC-level FMEA methodology to design in compliance with IEC61508	claim
25	144	Adaptive power management in energy harvesting systems	claim
26	143	Portable multimedia SoC design: a global challenge	claim
27	142	Optimizing instruction-set extensible processors under data bandwidth constraints	claim
28	141	Energy-efficient real-time task scheduling with task rejection	claim
29	139	Efficient high-performance ASIC implementation of JPEG-LS encoder	claim
30	138	An ADC-BiST scheme using sequential code analysis	claim
31	138	Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling	claim
32	138	Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems	claim
33	136	Compositional specification of behavioral semantics	claim
34	134	Accurate temperature-dependent integrated circuit leakage power estimation is easy	claim
35	134	Non-fractional parallelism in LDPC decoder implementations	claim
36	133	Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding	claim
37	133	Stochastic modeling and optimization for robust power management in a partially observable system	claim
38	130	A novel criticality computation method in statistical timing analysis	claim
39	130	Development of on board, highly flexible, Galileo signal generator ASIC	claim
40	128	Accounting for cache-related preemption delay in dynamic priority schedulability analysis	claim
41	127	A calculator for Pareto points	claim
42	126	Dynamic learning based scan chain diagnosis	claim
43	126	The ARTEMIS cross-domain architecture for embedded systems	claim
44	126	WAVSTAN: waveform based variational static timing analysis	claim
45	126	Design and DfT of a high-speed area-efficient embedded asynchronous FIFO	claim
46	126	A future of customizable processors: are we there yet?	claim
47	125	Simulation platform for UHF RFID	claim
48	125	Design space exploration of partially re-configurable embedded processors	claim
49	124	Worst-case design and margin for embedded SRAM	claim
50	123	Clock domain crossing fault model and coverage metric for validation of SoC design	claim
51	122	Industrial applications	claim
52	119	A smooth refinement flow for co-designing HW and SW threads	claim
53	119	Experimental evaluation of protections against laser-induced faults and consequences on fault modeling	claim
54	118	Statistical model order reduction for interconnect circuits considering spatial correlations	claim
55	118	An area optimized reconfigurable encryptor for AES-Rijndael	claim
56	118	System level assessment of an optical NoC in an MPSoC platform	claim
57	117	Rapid and accurate latch characterization via direct Newton solution of setup/hold times	claim
58	117	Resource prediction for media stream decoding	claim
59	116	Testable design for advanced serial-link transceivers	claim
60	114	Fast positive-real balanced truncation of symmetric systems using cross Riccati equations	claim
61	114	Performance aware secure code partitioning	claim
62	114	Mapping the physical layer of radio standards to multiprocessor architectures	claim
63	114	Two-level microprocessor-accelerator partitioning	claim
64	113	Congestion-controlled best-effort communication for networks-on-chip	claim
65	112	Compact hardware design of Whirlpool hashing core	claim
66	112	Tool-support for the analysis of hybrid systems and models	claim
67	112	Automatic synthesis of compressor trees: reevaluating large counters	claim
68	111	CATS: cycle accurate transaction-driven simulation with multiple processor simulators	claim
69	111	Cost-aware capacity optimization in dynamic multi-hop WSNs	claim
70	110	Reconfigurable system-on-chip data processing units for space imaging instruments	claim
71	110	Accurate timing analysis using SAT and pattern-dependent delay models	claim
72	110	Nonlinearity analysis of Analog/RF circuits using combined multisine and volterra analysis	claim
73	109	Microprocessors in the era of terascale integration	claim
74	109	System level clock tree synthesis for power optimization	claim
75	109	An efficient algorithm for online management of 2D area of partially reconfigurable FPGAs	claim
76	109	Area optimization of multi-cycle operators in high-level synthesis	claim
77	109	Toward a scalable test methodology for 2D-mesh Network-on-Chips	claim
78	108	A symbolic methodology for the verification of analog and mixed signal designs	claim
79	108	Speeding up SystemC simulation through process splitting	claim
80	108	Evaluation of design for reliability techniques in embedded flash memories	claim
81	107	Routing table minimization for irregular mesh NoCs	claim
82	107	Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow	claim
83	107	Design of high-resolution MOSFET-only pipelined ADCs with digital calibration	claim
84	107	Microarchitectural support for program code integrity monitoring in application-specific instruction set processors	claim
85	106	Optimized integration of test compression and sharing for SOC testing	claim
86	106	Design closure driven delay relaxation based on convex cost network flow	claim
87	106	Low-cost protection for SER upsets and silicon defects	claim
88	105	Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison	claim
89	105	Instruction-set customization for real-time embedded systems	claim
90	105	Understanding voltage variations in chip multiprocessors using a distributed power-delivery network	claim
91	105	A tiny and efficient wireless ad-hoc protocol for low-cost sensor networks	claim
92	104	Dynamic reconfiguration in sensor networks with regenerative energy sources	claim
93	103	Automatic application specific floating-point unit generation	claim
94	103	Flexible hardware reduction for elliptic curve cryptography in GF(2m)	claim
95	103	Fast and accurate routing demand estimation for efficient routability-driven placement	claim
96	102	A two-tone test method for continuous-time adaptive equalizers	claim
97	102	Accurate and scalable reliability analysis of logic circuits	claim
98	102	Efficient testbench code synthesis for a hardware emulator system	claim
99	102	Use of statistical timing analysis on real designs	claim
100	101	Polynomial-time subgraph enumeration for automated instruction set extension	claim
101	100	Life begins at 65: unless you are mixed signal?	claim
102	100	Working with process variation aware caches	claim
103	100	SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling	claim
104	100	Abstraction and refinement techniques in automated design debugging	claim
105	100	A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems	claim
106	99	Design challenges at 65nm and beyond	claim
107	99	Very wide register: an asymmetric register file organization for low power embedded processors	claim
108	99	Instruction trace compression for rapid instruction cache simulation	claim
109	99	A non-intrusive isolation approach for soft cores	claim
110	99	An efficient code compression technique using application-aware bitmask and dictionary selection methods	claim
111	98	Simulation-based reusable posynomial models for MOS transistor parameters	claim
112	98	A one-shot configurable-cache tuner for improved energy and performance	claim
113	97	Estimating functional coverage in bounded model checking	claim
114	97	Feasibility intervals for multiprocessor fixed-priority scheduling of arbitrary deadline periodic systems	claim
115	97	What if you could design tomorrow's system today?	claim
116	97	Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture	claim
117	96	Self-heating-aware optimal wire sizing under Elmore delay model	claim
118	96	An algorithm to minimize leakage through simultaneous input vector control and circuit modification	claim
119	95	Memory bank aware dynamic loop scheduling	claim
120	95	Event driven data processing architecture	claim
121	95	A multi-core debug platform for NoC-based systems	claim
122	94	A new technique for characterization of digital-to-analog converters in high-speed systems	claim
123	94	Register pointer architecture for efficient embedded processors	claim
124	94	Optimization-based wideband basis functions for efficient interconnect extraction	claim
125	93	Minimum-energy LDPC decoder for real-time mobile application	claim
126	93	Testing in the year 2020	claim
127	92	Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware	claim
128	92	Test quality analysis and improvement for an embedded asynchronous FIFO	claim
129	92	Dynamic power management under uncertain information	claim
130	92	Efficient nonlinear distortion analysis of RF circuits	claim
131	92	Enabling certification for dynamic partial reconfiguration using a minimal flow	claim
132	92	Slow write driver faults in 65nm SRAM technology: analysis and March test solution	claim
133	92	Random sampling of moment graph: a stochastic Krylov-reduction algorithm	claim
134	92	Layout-aware gate duplication and buffer insertion	claim
135	91	Transient fault prediction based on anomalies in processor events	claim
136	91	Remote testing and diagnosis of System-on-Chips using network management frameworks	claim
137	90	Bus access optimisation for FlexRay-based distributed embedded systems	claim
138	89	Computing synchronizer failure probabilities	claim
139	89	Cyclostationary feature detection on a tiled-SoC	claim
140	89	Mapping multi-dimensional signals into hierarchical memory organizations	claim
141	88	Improve CAM power efficiency using decoupled match line scheme	claim
142	88	Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming	claim
143	86	Reduction of detected acceptable faults for yield improvement via error-tolerance	claim
144	86	Thermally robust clocking schemes for 3D integrated circuits	claim
145	85	Timing simulation of interconnected AUTOSAR software-components	claim
146	85	Impact of process variations on multicore performance symmetry	claim
147	85	Low-power warp processor for power efficient high-performance embedded systems	claim
148	85	Scalable reconfigurable channel decoder architecture for future wireless handsets	claim
149	85	Efficient computation of the worst-delay corner	claim
150	85	QuteSAT: a robust circuit-based SAT solver for complex circuit structure	claim
151	84	On test generation by input cube avoidance	claim
152	83	Temperature and voltage aware timing analysis: application to voltage drops	claim
153	83	High-level test synthesis for delay fault testability	claim
154	81	Using the inter- and intra-switch regularity in NoC switch testing	claim
155	81	Improving utilization of reconfigurable resources using two dimensional compaction	claim
156	81	Formal verification of a pervasive interconnect bus system in a high-performance microprocessor	claim
157	80	Engineering trust with semantic guardians	claim
158	80	Low complexity LDPC code decoders for next generation standards	claim
159	80	Incremental ABV for functional validation of TL-to-RTL design refinement	claim
160	80	Microarchitecture floorplanning for sub-threshold leakage reduction	claim
161	80	A new hybrid solution to boost SAT solver performance	claim
162	80	Double-via-driven standard cell library design	claim
163	79	HW/SW implementation from abstract architecture models	claim
164	79	Utilization of SECDED for soft error and variation-induced defect tolerance in caches	claim
165	78	Hardware scheduling support in SMP architectures	claim
166	78	Low-g accelerometer fast prototyping for automotive applications	claim
167	77	A dynamically adaptive DSP for heterogeneous reconfigurable platforms	claim
168	77	Method for reducing jitter in multi-gigahertz ATE	claim
169	76	Hard real-time reconfiguration port scheduling	claim
170	76	Heterogeneous systems on chip and systems in package	claim
171	75	Efficient code density through look-up table compression	claim
172	74	Modeling and simulation alternatives for the design of networked embedded systems	claim
173	74	Re-configuration of sub-blocks for effective application of time domain tests	claim
174	74	Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks	claim
175	73	Design methods for security and trust	claim
176	72	Experimental validation of a tuning algorithm for high-speed filters	claim
177	72	The impact of loop unrolling on controller delay in high level synthesis	claim
178	71	Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL	claim
179	71	Task scheduling for reliable cache architectures of multiprocessor systems	claim
180	70	Reversible circuit technology mapping from non-reversible specifications	claim
181	69	Verification-guided soft error resilience	claim
182	68	Performance analysis of multimedia applications using correlated streams	claim
183	68	A sophisticated memory test engine for LCD display drivers	claim
184	68	Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip	claim
185	66	Yield-aware placement optimization	claim
186	65	Clock-frequency assignment for multiple clock domain systems-on-a-chip	claim
187	64	Maximum circuit activity estimation using pseudo-boolean satisfiability	claim
188	63	Efficient and scalable compiler-directed energy optimization for realtime applications	claim
189	56	Unknown blocking scheme for low control data volume and high observability	claim
190	55	Sensitivity analysis for fault-analysis and tolerance in RF front-end circuitry	claim
191	53	Synthesis of task and message activation models in real-time distributed automotive systems	claim

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