Dacota: Post-silicon validation of the memory subsystem in multi-core designs

The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules of modern processor designs. Recent trends towards chip multiprocessors (CMPs) are exacerbating the problem because of their complex and sometimes nondeterministic memory subsystems, prone to subtle but devastating bugs. This deteriorating situation calls for highefficiency, high-coverage results in functional validation, results that are be achieved by leveraging the performance of post-silicon validation, that is, those verification tasks that are executed directly on prototype hardware. The orders-of-magnitude faster testing in post-silicon enables designers to achieve much higher coverage before customer release, but only if the limitations of this technology in diagnosis and internal node observability could be overcome. In this work, we unlock the full performance of postsilicon validation through Dacot...

• Type: Conference
• Year: 2009
• Where: HPCA
• Authors: Andrew DeOrio, Ilya Wagner, Valeria Bertacco
• Keywords: Computer Architecture, Correct Memory Operation, HPCA 2009, Memory Subsystem Bugs, Nondeterministic Memory Subsystems