DAPR: Design Automation for Partially Reconfigurable FPGAs

Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requirements, increased performance, and increased functionality. However, since leveraging these additional benefits requires specific designer expertise, which increases design time, PR has not yet gained widespread usage. Even though Xilinx's PR design flow significantly eases PR design, to fully leverage PR benefits designers require extensive PR design flow knowledge, as well as low-level architectural details of the target FPGA device. In this paper, we present a PR design flow and associated tool to automate PR design intricacies and design space exploration. Our design flow and tool can significantly reduce PR design time effort and make PR designs more accessible and amenable to a wider range of PR designers.

• Type: Journal
• Year: 2010
• Where: ERSA
• Authors: Shaon Yousuf, Ann Gordon-Ross
• Keywords: ERSA 2010, Hardware, PR Design, PR Design Flow, PR Design Time