Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures

The recent design shift towards multicore processors has spawned a significant amount of research in the area of program parallelization. The future abundance of cores on a single chip requires programmer and compiler intervention to increase the amount of parallel work possible. Much of the recent work has fallen into the areas of coarse-grain parallelization: new programming models and different ways to exploit threads and data-level parallelism. This work focuses on a complementary direction, improving performance through automated fine-grain parallelization. The main difficulty in achieving a performance benefit from fine-grain parallelism is the distribution of data memory accesses across the data caches of each core. Poor choices in the placement of data accesses can lead to increased memory stalls and low resource utilization. We propose a profile-guided method for partitioning memory accesses across distributed data caches. First, a profile determines affinity relation...

• Type: Conference
• Year: 2007
• Where: MICRO
• Authors: Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke
• Keywords: Data Accesses, Data Caches, Hardware, Memory Accesses, MICRO 2007