Data marshaling for multi-core architectures

Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to best run that segment, can improve performance and save power. However, SE’s benefit is limited because most segments access inter-segment data, i.e., data generated by the previous segment. When consecutive segments run on different cores, accesses to inter-segment data incur cache misses, thereby reducing performance. This paper proposes Data Marshaling (DM), a new technique to eliminate cache misses to inter-segment data. DM uses profiling to identify instructions that generate inter-segment data, and adds only 96 bytes/core of storage overhead. We show that DM significantly improves the performance of two promising Staged Execution models, Accelerated Critical Sections and producer-consumer pipeline parallelism, on both homogeneous and heterogeneous multi-core systems. In both models, DM can achieve alm...

• Type: Conference
• Year: 2010
• Where: ISCA
• Authors: M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt
• Keywords: Cache Misses, Data Incur Cache, Hardware, Inter-segment Data, ISCA 2010