ISCA 2010 - PDF Preprint Papers

ISCA 2010 International Symposium on Computer Architecture

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ISCA
2010
IEEE

413views Hardware» more ISCA 2010»

Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing

14 years 4 months ago

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As CMOS scales beyond the 45nm technology node, leakage concerns are starting to limit microprocessor performance growth. To keep dynamic power constant across process generations...

Xiaochen Guo, Engin Ipek, Tolga Soyata

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Id	Views	Title	Status

1	413	Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing	claim
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3	340	Necromancer: enhancing system throughput by animating dead cores	claim
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5	314	Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis	claim
6	305	Rethinking DRAM design and organization for energy-constrained multi-cores	claim
7	292	Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications	claim
8	284	Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping	claim
9	247	An integrated GPU power and performance model	claim
10	240	Modeling critical sections in Amdahl's law and its implications for multicore design	claim
11	239	Sentry: light-weight auxiliary memory access control	claim
12	237	High performance cache replacement using re-reference interval prediction (RRIP)	claim
13	236	Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors	claim
14	232	Data marshaling for multi-core architectures	claim
15	232	Evolution of thread-level parallelism in desktop applications	claim
16	231	The rebirth of neural networks	claim
17	229	Understanding sources of inefficiency in general-purpose chips	claim
18	222	Cohesion: a hybrid memory model for accelerators	claim
19	219	Using hardware vulnerability factors to enhance AVF analysis	claim
20	216	The impact of management operations on the virtualized datacenter	claim
21	214	Re-architecting DRAM memory systems with monolithically integrated silicon photonics	claim
22	214	Translation caching: skip, don't walk (the page table)	claim
23	210	An intra-chip free-space optical interconnect	claim
24	205	The virtual write queue: coordinating DRAM and last-level cache policies	claim
25	204	Energy proportional datacenter networks	claim
26	199	A case for FAME: FPGA architecture model execution	claim
27	199	Use ECP, not ECC, for hard failures in resistive memories	claim
28	192	NoHype: virtualized cloud infrastructure without the virtualization	claim
29	189	RETCON: transactional repair without replay	claim
30	188	Guest Editor's Note	claim
31	185	Dynamic warp subdivision for integrated branch and memory divergence tolerance	claim
32	181	ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations	claim
33	176	Forwardflow: a scalable core for power-constrained CMPs	claim
34	170	Relax: an architectural framework for software recovery of hardware faults	claim
35	163	WiDGET: Wisconsin decoupled grid execution tiles	claim
36	143	Web search using mobile cores: quantifying and mitigating the price of efficiency	claim
37	131	Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races	claim

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