Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding

Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic to include specifications for decimal floating-point arithmetic and IBM recently announced incorporating a decimal floatingpoint unit into their POWER6 processor. As processor support for decimal floating-point arithmetic emerges, it is important to investigate efficient algorithms and hardware designs for common decimal floating-point arithmetic algorithms. This paper presents novel designs for a decimal floating-pointadder and a decimal floating-point multifunction unit. To reduce their delay, both the adder and the multifunction unit use decimal injection-based rounding, a new form of decimal operand alignment, and a fast flag-based method for rounding and overflow detection. Synthesis results indicate that the proposed adder is roughly 21% faster

• Type: Conference
• Year: 2007
• Where: ARITH
• Authors: Liang-Kai Wang, Michael J. Schulte
• Keywords: Applied Computing, ARITH 2007, Decimal Operand Alignment, Decimal floating-point Multifunction, Decimal floatingpoint Unit