A decoupled KILO-instruction processor

Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elusive goal. Traditional processors are composed of structures that do not scale to large instruction windows because of timing and power constraints. However, the behavior of programs executed with large instruction windows gives rise to a natural and simple alternative to scaling. We characterize this phenomenonof execution locality and propose a microarchitecture to exploit it to achieve the benefit of a large instruction window processor with low implementation cost. Execution locality is the tendency of instructions to exhibit high or low latency based on their dependence on memory operations. In this paper we propose a decoupled microarchitecture that executes low latency instructions on a Cache Processor and high latency instructions on a Memory Processor. We demonstrate that such a design, using small s...

• Type: Conference
• Year: 2006
• Where: HPCA
• Authors: Miquel Pericàs, Adrián Cristal, Ruben Gonzalez, Daniel A. Jiménez, Mateo Valero
• Keywords: Computer Architecture, HPCA 2006, Instruction Window Processor, Large Instruction Windows, Low Latency Instructions