HPCA 2006 - PDF Preprint Papers

HPCA 2006 International Symposium on High-Performance Computer Architecture

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HPCA
2006
IEEE

334views Distributed And Parallel Com...» more HPCA 2006»

An approach for implementing efficient superscalar CISC processors

14 years 11 months ago

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An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...

Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...

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Id	Views	Title	Status

1	334	An approach for implementing efficient superscalar CISC processors	claim
2	195	BulletProof: a defect-tolerant CMP switch architecture	claim
3	185	Phase characterization for power: evaluating control-flow-based and event-counter-based techniques	claim
4	182	InfoShield: a security architecture for protecting information usage in memory	claim
5	181	Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads	claim
6	173	The common case transactional behavior of multithreaded programs	claim
7	165	High performance file I/O for the Blue Gene/L supercomputer	claim
8	158	Dynamic power-performance adaptation of parallel computation on chip multiprocessors	claim
9	155	Reducing resource redundancy for concurrent error detection techniques in high performance microprocessors	claim
10	150	CORD: cost-effective (and nearly overhead-free) order-recording and data race detection	claim
11	148	Probabilistic counter updates for predictor hysteresis and stratification	claim
12	146	Construction and use of linear regression models for processor performance analysis	claim
13	136	Completely verifying memory consistency of test program executions	claim
14	135	LogTM: log-based transactional memory	claim
15	133	Exploiting parallelism and structure to accelerate the simulation of chip multi-processors	claim
16	130	CMP design space exploration subject to physical constraints	claim
17	126	A decoupled KILO-instruction processor	claim
18	116	DMA-aware memory energy management	claim
19	115	Retention-aware placement in DRAM (RAPID): software methods for quasi-non-volatile DRAM	claim
20	113	New architectures for a new biology	claim
21	110	Increasing the cache efficiency by eliminating noise	claim
22	107	Store vectors for scalable memory dependence prediction and scheduling	claim
23	104	Software-hardware cooperative memory disambiguation	claim
24	103	Understanding the performance-temperature interactions in disk I/O of server workloads	claim
25	95	Efficient instruction schedulers for SMT processors	claim
26	95	Speculative synchronization and thread management for fine granularity threads	claim
27	82	ReViveI/O: efficient handling of I/O in highly-available rollback-recovery servers	claim

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