Depth-driven verification of simultaneous interfaces

The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This trend is accelerated with the advent of highly integrated systemon-a-chip (SoC) designs, which feature multiple complex subcomponents connected by simultaneously active interfaces. In this paper, we introduce a closed-loop feedback technique targeting the verification of multiple components connected by parallel interfaces. We utilize an environment with hierarchical Markov models, where top-level submodels specify overarching simulation goals of the system, while lower-level submodels specify the detailed component-level input generation. Test accuracy is improved through the use of depth-driven random test generation. The approach allows users to specify correctness properties and key activity nodes in the design to be exercises. We examine three non-trivial designs, two microprocessors and a chipmultiproces...

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Ilya Wagner, Valeria Bertacco, Todd M. Austin
• Keywords: ASPDAC 2006, Closed-loop Feedback Technique, Hardware, Test Generation, Test Generation Technique