On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler

Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are shared by some or all of the cores on the chip. Prior work has presented methods for improving the performance of such caches when scheduling soft real-time workloads. Given these methods, two additional research issues arise: (1) how to automatically profile the cache behavior of real-time tasks within the scheduler; and (2) how to implement scheduling methods efficiently, so that scheduling overheads do not offset any cache-related performance gains. This paper addresses these two issues in an implementation of a cacheaware soft real-time scheduler within Linux, and shows that the use of this scheduler can result in performance improvements that directly result from a decrease in shared cache miss rates.

• Type: Journal
• Year: 2009
• Where: ECRTS
• Authors: John M. Calandrino, James H. Anderson
• Keywords: Chip, ECRTS 2009, Embedded Systems, Soft Real-time, Soft Real-time Workloads