The design and implementation of a low-latency on-chip network

— Many of the issues that will be faced by the designers of multi-billion transistor chips may be alleviated by the presence of a flexible global communication infrastructure. In the short term, such a network will provide scalable chip-wide communication and ease the complexity of handling multi-cycle communications. In the long term, the network will become a primary tool for optimising power and data transfers and for scheduling computations. This paper details the design and implementation of a low-latency on-chip network. The network’s speculative routers are in the best case able to route flits in a single clock cycle, helping to minimise on-chip communication latencies and maximise the effectiveness of buffering resources. Results from our 180nm test chip demonstrate an inter-router data transfer rate in excess of 16Gbit/s for each link. In the best case each router hop adds just 1 clock cycle to the final communication latency.

• Type: Conference
• Year: 2006
• Where: ASPDAC
• Authors: Robert D. Mullins, Andrew West, Simon W. Moore
• Keywords: ASPDAC 2006, Communication, Low-latency On-chip Network, On-chip Communication Latencies